DESIGN OF LOW POWER 2-D MULTIPLIER USING 2-D BYPASSING TECHNIQUE
نویسندگان
چکیده
منابع مشابه
Low Power Multiplier to Reduce Switching Activities Using Bypassing Technique
Multipliers and adders are the basic circuits required for implementing any Arithmetic and logic functions in VLSI. Many of the real-time applications like the arithmetic operations in Microprocessor, the filter designing in Signal processing require the multipliers. As the multipliers play a major role in the VLSI designing the power consumption related to them is a parameter to be thought of....
متن کاملLow Power Multiplier Design with Improved Column Bypassing Scheme
Power, speed and area are prime design constraints for portable electronics devices and signal processing applications. Multiplier plays an important role in DSP applications. In this paper, a low power and high speed multiplier with improved column bypassing scheme is presented. Primary power reduction is obtained by disabling the supply voltage of non-functional blocks when the operands of th...
متن کاملArea Efficient Low Power Vedic Multiplier Design Using GDI Technique
Multipliers consume maximum amount of power during the partial product addition. For higher order multiplication, a huge number of adders are used to perform the partial product addition. Using compressor adders, that can add four, five , six or seven bits at a time, the number of full adders and half adders can be reduced and thus area and power consumed also gets reduced. These compressor add...
متن کاملHigh Speed and Low Power Multiplier Design Using Mtcmos Technique
MTCMOS is an effective circuit level technique which has multiple threshold voltages in order to optimize delay and power. Low threshold voltage MOSFETs enhance the speed performance, while the high threshold voltages MOSFETs minimize the static leakage power. The above technique is adopted in parallel multiplier with level shifter interface which gives supply voltage for MTCMOS transistors. By...
متن کاملDesign of Low Power 2-D Dct Architecture Using Reconfigurable Architecture
This Research paper includes designing a area efficient and low error Discrete Cosine Transform. This area efficient and low error DCT is obtained by using shifters and adders in place of multipliers. The main technique used here is CSD(Canonical Sign Digit) technique.CSD technique efficiently reduces redundant bits. Pipelining technique is also introduced here which reduces the processing time.
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal on Intelligent Electronic Systems
سال: 2013
ISSN: 0973-9238
DOI: 10.18000/ijies.30130